1. Field of the Invention
The present invention relates to a method and apparatus for carrying out fault diagnosis for integrated logic circuits (or “circuits” hereafter), to achieve high diagnostic resolution even in the presence of complex, dynamic, and/or multiple defects, all inevitable in deep-submicron circuits.
2. Description of the Related Art
Failure analysis is the process of localizing physical defects in a failing circuit and identifying their root causes. Failure analysis is indispensable for silicon debugging, yield improvement, and reliability enhancement. The key part in the failure analysis is defect localization, which is achieved by first using a fault diagnosis procedure to identify suspicious areas in a failing circuit and then using physical inspection means, such as an electron beam (EB) tester to search in the identified suspicious areas for actual defects.
Fault diagnosis is the process of identifying suspicious areas in a failing circuit by making use of logical faults assumed in a circuit model. A logical fault has two attributes: location and logical behavior. In a gate-level circuit model, the location attribute is one or more nets or pins, and the logical behavior attribute is one or more logic values. Fault modeling defines these attributes in a general manner. The process of identifying faults, with likely link to physical defects, is known as fault diagnosis. Physical defects can be characterized from three aspects: complexity (simple or complex), temporality (static or dynamic), and cardinality (single or multiple). A simple defect forces a single site to a fixed logic value of 0 or 1. A complex defect, such as a resistive short or open, causes multiple effects around the defect site. For example, a complex defect in a fanout gate forces its output to an intermediate voltage and multiple faulty logic values may appear at its fanout branches depending on the threshold voltages of the branches (see: D. Lavo, T. Larrabee, and B. Chess, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis”, Proc. Intl. Test Conf., pp. 611-619, 1996). Such a complex defect is called a Byzantine defect in this paper, A static defect shows the same behavior for all input vectors, while a dynamic defect changes its behavior for different input vectors because the strength of a signal can vary for different input conditions. Finally, a circuit may contain a single defect or multiple defects.
Based on this defect classification, the defect scenario of a failing circuit can be trivial or non-trivial. The existence of a simple, static, and single defect is a trivial defect scenario, whereas the existence of complex, dynamic, or multiple defects is a non-trivial defect scenario.
In a trivial defect scenario, the failing circuit has exactly one constant defective effect at one location. Techniques based on the single stuck-at fault model, which assume a line to be fixed at a logic value of 0 or 1, can readily achieve accurate diagnosis for this scenario.
In reality, a failing circuit is more likely to have a nontrivial defect scenario. In this case, the circuit either has defective effects at multiple locations or the behavior of a defect changes for different input vectors. Obviously, the single stuck-at fault model cannot represent physical defects of this type, and accurate fault diagnosis is generally difficult to achieve.
The defect complexity issue in a non-trivial defect scenario has been addressed by using a combination of simple fault models or by using a realistic fault model. For example, a technique (see: S. Venkataraman and S. Drummonds, “POIROT: A Logic Fault Diagnosis Tool and Its Applications”, Proc. Intl. Test Conf., pp. 253-262, 2000) uses four fault models to cover various defects. On the other hand, various realistic fault models, such as stuck-open (see: S. Venkataraman and S. Drummonds, “POIROT. A Logic Fault Diagnosis Tool and Its Applications”, Proc. Intl. Test Conf., pp. 253-262, 2000), bridging (see: S. D. Millman, E. J. McCluskey, and J. M. Acken, “Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries”, Proc. Intl. Test Conf., pp. 860-870, 1990; P. Maxwell and R. Aiken, “Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds”, Proc. Intl. Test Conf., pp. 63-72, 1993.), transistor leakage (W. Mao and R. K. Gulati, “QUIETEST: A Quiescent Current Testing Methodology for Detecting Short Faults”, Proc. ICCAD' 90, pp. 280-283, November 1990), and Byzantine (see: D. Lavo, T. Larrabee, and B. Chess, “Beyond the Byzantine Generals: Unexpected Behavior and Bridging Fault Diagnosis”, Proc. Intl. Test Conf., pp. 611-619, 1996; S. Huang, “Speeding Up the Byzantine Fault Diagnosis Using Symbolic Simulation”, Proc. VLSI Test Symp., pp. 193-198, 2002), to better reflect actual defect mechanisms.
The defect cardinality issue in a non-trivial defect scenario has been addressed (see: M. Abramovici and M. Breuer, Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis, IEEE Trans. on Comp., vol. 29, no. 6, pp. 451-460, 1980; H. Cox and J. Rajski, “A Method of Fault Analysis for Test Generation and Fault Diagnosis”, IEEE Trans. On Computer-Aided Design, vol. 7, no. 7, pp. 813-833, 1988; H. Takahashi, K. O. Boateng, K. K Saluja, and Y. Takamatsu, “On Diagnosing Multiple Stuck-At Faults Using Multiple and Single Fault Simulation”, IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 362-368, 2002), all by targeting multiple tuck-at faults.
Recently, per-test fault diagnosis is gaining popularity in fault diagnosis for a non-trivial defect scenario. Per-test means that failing vectors are processed one at a time. The basic idea is that only one of the multiple defects in a circuit may be activated by one failing vector in some cases. As a result, a single fault model can be assumed for the activated defect and a relatively easy fault diagnosis procedure based on single fault simulation can be used for a non-trivial defect scenario. Thus, per-test fault diagnosis addresses both temporality and cardinality issues, and has been shown to be highly effective for a non-trivial defect scenario.
A prior art per-test method uses the single stuck-at fault model (see: T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, “Diagnosing Combinational Logic Designs Using the Single Location At-a-Time (SLAT) Paradigm” Proc. Intl. Test Conf., pp. 287-296, 2001). Like other per-test fault diagnosis methods, this method is based on two assumptions. The first assumption is that even when multiple defects exist, the simulated output response of a circuit with an assumed single fault may match the actual output response of the corresponding failing circuit under a certain failing input vector. Such a failing input vector is called a SLAT vector. The second assumption is that if the simulated output response of a circuit with an assumed single fault matches the actual output response under a SLAT vector, the possibility that the fault actually links to a physical defect is high. The advantage of the per-test fault diagnosis method is that a single fault model can be used in fault diagnosis for dynamic and multiple defects.
Several other per-test fault diagnosis methods have been proposed (see: S. Venkataraman and S. Drummonds, “POIROT: A Logic Fault Diagnosis Tool and Its Applications”, Proc. Intl. Test Conf., pp. 263-262, 2000; J. Waicukauski and E. Lindbloom, “Failure Diagnosis of Structured Circuits”, IEEE Design and Test of Comp., vol. 6, no. 4, pp. 49-60, 1989; D. Lavo, I. Hartanto, and T. Larrabee, “Multiplets, Models and the Search for Meaning”, Proc. Intl. Test Conf., pp. 250-259, 2002). The single stuck-at fault model is used in the above-mentioned documents of Waicukauski et al., Bartenstein et al. and Lavo et al., while a combination of stuck-at, stuck-open, net, and bridging faults is used in the document of Venkataraman et al. These methods attempt to find a minimal set of faults that explains as many failing vectors as possible. Such a fault set is called a multiplet in the document of Bartenstein et al.
However, the diagnostic resolution or accuracy of the above-mentioned prior art per-test fault diagnosis method is often low for a circuit with complex defects. The major reason is that the single stuck-at fault model cannot accurately represent the logic behaviors of complex defects, such as Byzantine defects. In addition, a simple criterion is used for matching simulated output responses and actual output responses, which often results in diagnostic information loss, leading to misdiagnosis. All these disadvantages contribute to significantly increased cost and time of failure analysis. As a result, there is a strong need to propose a new per-test fault method that can achieve high diagnostic resolution even in the presence of complex, dynamic, and multiple defects.